- Table of contents
- 3. Error Correcting Codes
3. Error Correcting Codes¶
The design of a digital communication system aims to maximize the transmission bit rate, to minimize the probability of bit error, to minimize the required power, or equivalently, to minimize the required carrier-to-noise ratio, to minimize the required system bandwidth and to minimize the system complexity and cost. Satellite Digital Video Broadcasting (DVB) systems are particularly affected by power limitations, therefore ruggedness against noise and interference should be the main design objective, rather than spectrum efficiency [1, 2]. In order to achieve high power efficiency without excessively penalizing the spectrum efficiency, such a system should use noise resistant types of modulation and effective channel codes. Recent trends in satellite communications show an increasing demand of higher-order M-ary modulation schemes. Higher-order M-ary modulation schemes can provide greater spectral efficiency and thus the high data rate required for either digital multimedia applications or other applications such as point-to-point high data rate backbone connectivity and future Earth observation missions requiring downlink data rates exceeding 1 Gbps .
BCH codes fall into the group of block codes, where the digital information is transmitted in packets of a K symbols length. Each symbol consists of n bits, and the greatest applicability belongs to the dual BCH codes, where n = 1. The BCH codes are generally represented as BCH, where N is the total number of coded symbols in a packet, and T is the number of repairable symbol errors. For the most common codes N = 2h – 1, where h can be every number which is greater than or equals to 3, and hT = N−K is the number of error protection symbols, or checksum .
3.2 Low Density Parity Check¶
An LDPC code consists of a sparse matrix with very few ones in each row and column, called the “Parity Check Matrix”. Usually, each row of the matrix is designed to be linearly independent from the other rows. Regular codes have an equal number of non-zero elements in each column and an equal number in each row, while irregular codes can have a varying number .
When multiplied by a column vector “codeword” in modulo 2 arithmetic, the result should be a column vector of 0’s. The code word consists of a block of “parity” check bits, which has the same length as the number of rows, and a block of data bits. The rate of the code is the number of data bits divided by the number of columns in the matrix. The process of encoding is determining the set of parity bits that, when concatenated with the data bits, will multiply the parity check matrix and create a column of zeros. The decoding process determines the set of bits that were transmitted with this property based on the received packet .
In some cases, LDPC codes can be constructed to have better performance than Turbo codes, another widely used error correction code. Additionally, LDPC codes are advantageous in that they use a lower complexity iterative decoding “belief propagation” algorithm which can be implemented in parallel in hardware. The decoder is also very good at detecting errors in the received codeword while also determining when it is unable to correctly decode the packet. Although the encoding complexity is somewhat high, the powerful properties of LDPC codes have warranted their inclusion in many standards such as IEEE 802.16, 802.20, 802.3 and DVB-RS2 .
 L. Jordanova, L.Laskov, D.Dobrev Influence of BCH and LDPC Code PArameters on the BER Characteristics of Satellie DVB Channels Engineering, Technology & Applied Science Research, Vol4, No 1, 2014 591-595
 David J. C. MacKay, Information Theory, Inference and Learning Algorithms Cambridge University, 2003
 T. K. Moon, Error Correcting Coding: Mathematical Methods and Algorithms New York: Wiley, 2005